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SubjectRe: [RFC v4 net-next 1/4] net: phy: add MediaTek PHY driver
Hi Qingfang,

Quoting DENG Qingfang <dqfext@gmail.com>:

> Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
> The initialization procedure is from the vendor driver, but due to lack
> of documentation, the function of some register values remains unknown.
>
> Signed-off-by: DENG Qingfang <dqfext@gmail.com>
> ---
> RFC v3 -> RFC v4:
> - Remove unused include.
>
> drivers/net/phy/Kconfig | 5 ++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/mediatek.c | 111 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 117 insertions(+)
> create mode 100644 drivers/net/phy/mediatek.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index a615b3660b05..edd858cec9ec 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY
> Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet
> Transceiver.
>
> +config MEDIATEK_PHY
> + tristate "MediaTek PHYs"
> + help
> + Supports the MediaTek switch integrated PHYs.
> +
> config MICREL_PHY
> tristate "Micrel PHYs"
> help
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index de683e3abe63..9ed7dbab7770 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -64,6 +64,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o
> obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
> obj-$(CONFIG_MARVELL_PHY) += marvell.o
> obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
> +obj-$(CONFIG_MEDIATEK_PHY) += mediatek.o
> obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
> obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
> obj-$(CONFIG_MICREL_PHY) += micrel.o
> diff --git a/drivers/net/phy/mediatek.c b/drivers/net/phy/mediatek.c
> new file mode 100644
> index 000000000000..1627b7c04345
> --- /dev/null
> +++ b/drivers/net/phy/mediatek.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +#include <linux/module.h>
> +#include <linux/phy.h>
> +
> +#define MTK_EXT_PAGE_ACCESS 0x1f
> +#define MTK_PHY_PAGE_STANDARD 0x0000
> +#define MTK_PHY_PAGE_EXTENDED 0x0001
> +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
> +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
> +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
> +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
> +
> +static int mtk_phy_read_page(struct phy_device *phydev)
> +{
> + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
> +}
> +
> +static int mtk_phy_write_page(struct phy_device *phydev, int page)
> +{
> + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
> +}
> +
> +static void mtk_phy_config_init(struct phy_device *phydev)
> +{
> + /* Disable EEE */
> + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);

For my EEE patch I changed this line to:

genphy_config_eee_advert(phydev);

So PHY EEE part is setup properly at boot, instead enable it manual
via ethtool.
This function also takes the DTS parameters "eee-broken-xxxx" in to
account while
setting-up the PHY.

> +
> + /* Enable HW auto downshift */
> + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
> +
> + /* Increase SlvDPSready time */
> + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
> + __phy_write(phydev, 0x10, 0xafae);
> + __phy_write(phydev, 0x12, 0x2f);
> + __phy_write(phydev, 0x10, 0x8fae);
> + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
> +
> + /* Adjust 100_mse_threshold */
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
> +
> + /* Disable mcc */
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
> +}
> +

Greats,

René


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