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    Subject[PATCH 5.11 113/210] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips
    Date
    From: Shengjiu Wang <shengjiu.wang@nxp.com>

    [ Upstream commit 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f ]

    The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz
    and sample rate is 44100Hz, with the configuration pllprescale=2,
    postscale=sysclkdiv=1, some chip may have wrong bclk
    and lrclk output with pll enabled in master mode, but with the
    configuration pllprescale=1, postscale=2, the output clock is correct.

    >From Datasheet, the PLL performs best when f2 is between
    90MHz and 100MHz when the desired sysclk output is 11.2896MHz
    or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice.

    So search available sysclk_divs from 2 to 1 other than from 1 to 2.

    Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search")
    Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
    Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
    Link: https://lore.kernel.org/r/1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    sound/soc/codecs/wm8960.c | 8 +++++++-
    1 file changed, 7 insertions(+), 1 deletion(-)

    diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
    index 660ec46eecf2..ceaf3bbb18e6 100644
    --- a/sound/soc/codecs/wm8960.c
    +++ b/sound/soc/codecs/wm8960.c
    @@ -707,7 +707,13 @@ int wm8960_configure_pll(struct snd_soc_component *component, int freq_in,
    best_freq_out = -EINVAL;
    *sysclk_idx = *dac_idx = *bclk_idx = -1;

    - for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
    + /*
    + * From Datasheet, the PLL performs best when f2 is between
    + * 90MHz and 100MHz, the desired sysclk output is 11.2896MHz
    + * or 12.288MHz, then sysclkdiv = 2 is the best choice.
    + * So search sysclk_divs from 2 to 1 other than from 1 to 2.
    + */
    + for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) {
    if (sysclk_divs[i] == -1)
    continue;
    for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
    --
    2.30.2


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