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    Subject[PATCH V6 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    The PMU capabilities are different among hybrid PMUs. Perf should dump
    the PMU capabilities information for each hybrid PMU.

    Factor out x86_pmu_show_pmu_cap() which shows the PMU capabilities
    information. The function will be reused later when registering a
    dedicated hybrid PMU.

    Reviewed-by: Andi Kleen <ak@linux.intel.com>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    ---
    arch/x86/events/core.c | 25 ++++++++++++++++---------
    arch/x86/events/perf_event.h | 3 +++
    2 files changed, 19 insertions(+), 9 deletions(-)

    diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
    index fe811b5..bb375ab 100644
    --- a/arch/x86/events/core.c
    +++ b/arch/x86/events/core.c
    @@ -1977,6 +1977,20 @@ static void _x86_pmu_read(struct perf_event *event)
    x86_perf_event_update(event);
    }

    +void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
    + u64 intel_ctrl)
    +{
    + pr_info("... version: %d\n", x86_pmu.version);
    + pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
    + pr_info("... generic registers: %d\n", num_counters);
    + pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
    + pr_info("... max period: %016Lx\n", x86_pmu.max_period);
    + pr_info("... fixed-purpose events: %lu\n",
    + hweight64((((1ULL << num_counters_fixed) - 1)
    + << INTEL_PMC_IDX_FIXED) & intel_ctrl));
    + pr_info("... event mask: %016Lx\n", intel_ctrl);
    +}
    +
    static int __init init_hw_perf_events(void)
    {
    struct x86_pmu_quirk *quirk;
    @@ -2037,15 +2051,8 @@ static int __init init_hw_perf_events(void)

    pmu.attr_update = x86_pmu.attr_update;

    - pr_info("... version: %d\n", x86_pmu.version);
    - pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
    - pr_info("... generic registers: %d\n", x86_pmu.num_counters);
    - pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
    - pr_info("... max period: %016Lx\n", x86_pmu.max_period);
    - pr_info("... fixed-purpose events: %lu\n",
    - hweight64((((1ULL << x86_pmu.num_counters_fixed) - 1)
    - << INTEL_PMC_IDX_FIXED) & x86_pmu.intel_ctrl));
    - pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
    + x86_pmu_show_pmu_cap(x86_pmu.num_counters, x86_pmu.num_counters_fixed,
    + x86_pmu.intel_ctrl);

    if (!x86_pmu.read)
    x86_pmu.read = _x86_pmu_read;
    diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
    index f04be6b..8523700 100644
    --- a/arch/x86/events/perf_event.h
    +++ b/arch/x86/events/perf_event.h
    @@ -1093,6 +1093,9 @@ void x86_pmu_enable_event(struct perf_event *event);

    int x86_pmu_handle_irq(struct pt_regs *regs);

    +void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
    + u64 intel_ctrl);
    +
    extern struct event_constraint emptyconstraint;

    extern struct event_constraint unconstrained;
    --
    2.7.4
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