Messages in this thread | | | Subject | Re: [PATCH 2/4] mips: bmips: add BCM63268 timer reset definitions | From | Álvaro Fernández Rojas <> | Date | Sun, 7 Mar 2021 11:08:20 +0100 |
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Hi Rob,
El 06/03/2021 a las 22:17, Rob Herring escribió: > On Thu, Feb 25, 2021 at 08:41:59PM +0100, Álvaro Fernández Rojas wrote: >> Add missing timer reset definitions for BCM63268. >> >> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> >> --- >> include/dt-bindings/reset/bcm63268-reset.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h >> index 6a6403a4c2d5..d87a7882782a 100644 >> --- a/include/dt-bindings/reset/bcm63268-reset.h >> +++ b/include/dt-bindings/reset/bcm63268-reset.h >> @@ -23,4 +23,8 @@ >> #define BCM63268_RST_PCIE_HARD 17 >> #define BCM63268_RST_GPHY 18 >> >> +#define BCM63268_TRST_SW 29 >> +#define BCM63268_TRST_HW 30 >> +#define BCM63268_TRST_POR 31 > > Numbering should be local to the provider, so shouldn't this be 0-2? > Unless these numbers correspond to something in the h/w (bit positions > for example).
Numbering corresponds to bit positions in the HW: uint32 ClkRstCtl; #define POR_RESET_STATUS (1 << 31) #define HW_RESET_STATUS (1 << 30) #define SW_RESET_STATUS (1 << 29) #define USB_REF_CLKEN (1 << 18) #define UTO_EXTIN_CLKEN (1 << 17) #define UTO_CLK50_SEL (1 << 16) #define FAP2_PLL_CLKEN (1 << 15) #define FAP2_PLL_FREQ_SHIFT 12 #define FAP1_PLL_CLKEN (1 << 11) #define FAP1_PLL_FREQ_SHIFT 8 #define WAKEON_DSL (1 << 7) #define WAKEON_EPHY (1 << 6) #define DSL_ENERGY_DETECT_ENABLE (1 << 4) #define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3) #define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2) #define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1) #define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0)
http://datashed.science/misc/bcm/gpl/broadcom-sdk-416L05/shared/opensource/include/bcm963xx/63268_map_part.h
> >> + >> #endif /* __DT_BINDINGS_RESET_BCM63268_H */ >> -- >> 2.20.1 >>
Best regards, Álvaro.
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