Messages in this thread | | | Subject | Re: [PATCH] KVM: x86/vPMU: Forbid reading from MSR_F15H_PERF MSRs when guest doesn't have X86_FEATURE_PERFCTR_CORE | From | Paolo Bonzini <> | Date | Tue, 30 Mar 2021 19:10:30 +0200 |
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On 29/03/21 14:48, Vitaly Kuznetsov wrote: > MSR_F15H_PERF_CTL0-5, MSR_F15H_PERF_CTR0-5 MSRs have a CPUID bit assigned > to them (X86_FEATURE_PERFCTR_CORE) and when it wasn't exposed to the guest > the correct behavior is to inject #GP an not just return zero. > > Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> > --- > arch/x86/kvm/x86.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index fe806e894212..125453155ede 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -3381,6 +3381,12 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > msr_info->data = 0; > break; > case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: > + if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) > + return kvm_pmu_get_msr(vcpu, msr_info); > + if (!msr_info->host_initiated) > + return 1; > + msr_info->data = 0; > + break; > case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: > case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: > case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: >
Queued to kvm/next, thanks (the write side goes to kvm/master instead).
Paolo
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