Messages in this thread | | | Date | Mon, 29 Mar 2021 22:54:18 -0700 (PDT) | Subject | Re: [PATCH] riscv,entry: fix misaligned base for excp_vect_table | From | Palmer Dabbelt <> |
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On Wed, 17 Mar 2021 01:17:25 PDT (-0700), yuzihao@ict.ac.cn wrote: > * In RV64, the size of each entry in excp_vect_table is 8 bytes. If the > base of the table is not 8-byte aligned, loading an entry in the table > will raise a misaligned exception. Although such exception will be > handled by opensbi/bbl, this still causes performance degradation. > > Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn> > --- > arch/riscv/kernel/entry.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 744f3209c..76274a4a1 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -447,6 +447,7 @@ ENDPROC(__switch_to) > #endif > > .section ".rodata" > + .align LGREG > /* Exception vector table */ > ENTRY(excp_vect_table) > RISCV_PTR do_trap_insn_misaligned
Thanks, this is on fixes.
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