Messages in this thread | | | Date | Tue, 30 Mar 2021 23:34:28 +0530 | From | Vinod Koul <> | Subject | Re: [PATCH v3 0/6] AM64: Add SERDES driver support |
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On 10-03-21, 17:38, Kishon Vijay Abraham I wrote: > AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't > have a clock generator (unlike J7200 base board). Here the clock from > the SERDES has to be routed to the PCIE connector. This series adds > support to drive reference clock output from SERDES and also adds > SERDES (torrent) and SERDES wrapper (WIZ) bindings. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [3] > > Changes from v2: > *) Sent the DT bindings as a separate series [4] > *) Remove enabling PHY output clock in isolation mode > > Changes from v1: > *) Model the internal clocks without device tree input (Add #clock-cells > to SERDES DT nodes for getting a reference to the clock using index > to phandle). This is in accordance with comment given by Rob [2]. > However the existing method to model clocks from device tree is not > removed to support upstreamed device tree. > *) Included a patch to fix modifying static data by instance specific > initializations. > *) Added a fix to delete "clk_div_sel" clk provider during cleanup
Applied, thanks
-- ~Vinod
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