Messages in this thread | | | Subject | Re: I915 CI-run with kfence enabled, issues found | From | Dave Hansen <> | Date | Mon, 29 Mar 2021 14:03:40 -0700 |
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On 3/29/21 10:45 AM, Marco Elver wrote: > On Mon, 29 Mar 2021 at 19:32, Dave Hansen <dave.hansen@intel.com> wrote: > Doing it to all CPUs is too expensive, and we can tolerate this being > approximate (nothing bad will happen, KFENCE might just miss a bug and > that's ok). ... >> BTW, the preempt checks in flush_tlb_one_kernel() are dependent on KPTI >> being enabled. That's probably why you don't see this everywhere. We >> should probably have unconditional preempt checks in there. > > In which case I'll add a preempt_disable/enable() pair to > kfence_protect_page() in arch/x86/include/asm/kfence.h.
That sounds sane to me. I'd just plead that the special situation (not needing deterministic TLB flushes) is obvious. We don't want any folks copying this code.
BTW, I know you want to avoid the cost of IPIs, but have you considered any other low-cost ways to get quicker TLB flushes? For instance, you could loop over all CPUs and set cpu_tlbstate.invalidate_other=1. That would induce a context switch at the next context switch without needing an IPI.
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