lkml.org 
[lkml]   [2021]   [Mar]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: I915 CI-run with kfence enabled, issues found
From
Date
On 3/29/21 10:45 AM, Marco Elver wrote:
> On Mon, 29 Mar 2021 at 19:32, Dave Hansen <dave.hansen@intel.com> wrote:
> Doing it to all CPUs is too expensive, and we can tolerate this being
> approximate (nothing bad will happen, KFENCE might just miss a bug and
> that's ok).
...
>> BTW, the preempt checks in flush_tlb_one_kernel() are dependent on KPTI
>> being enabled. That's probably why you don't see this everywhere. We
>> should probably have unconditional preempt checks in there.
>
> In which case I'll add a preempt_disable/enable() pair to
> kfence_protect_page() in arch/x86/include/asm/kfence.h.

That sounds sane to me. I'd just plead that the special situation (not
needing deterministic TLB flushes) is obvious. We don't want any folks
copying this code.

BTW, I know you want to avoid the cost of IPIs, but have you considered
any other low-cost ways to get quicker TLB flushes? For instance, you
could loop over all CPUs and set cpu_tlbstate.invalidate_other=1. That
would induce a context switch at the next context switch without needing
an IPI.

\
 
 \ /
  Last update: 2021-03-29 23:05    [W:0.070 / U:1.664 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site