Messages in this thread | | | Date | Sat, 27 Mar 2021 15:45:44 +0100 | From | Andrew Lunn <> | Subject | Re: [PATCH net-next,v2] net: dsa: mt7530: clean up core and TRGMII clock setup |
| |
On Fri, Mar 26, 2021 at 11:07:52PM -0700, Ilya Lipnitskiy wrote: > Three minor changes: > > - When disabling PLL, there is no need to call core_write_mmd_indirect > directly, use the core_write wrapper instead like the rest of the code > in the function does. This change helps with consistency and > readability. Move the comment to the definition of > core_read_mmd_indirect where it belongs. > > - Disable both core and TRGMII Tx clocks prior to reconfiguring. > Previously, only the core clock was disabled, but not TRGMII Tx clock. > So disable both, then configure them, then re-enable both, for > consistency. > > - The core clock enable bit (REG_GSWCK_EN) is written redundantly three > times. Simplify the code and only write the register only once at the > end of clock reconfiguration to enable both core and TRGMII Tx clocks. > > Tested on Ubiquiti ER-X running the GMAC0 and MT7530 in TRGMII mode. > > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Thanks for moving the comment.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
| |