Messages in this thread | | | Date | Thu, 25 Mar 2021 15:27:20 +0100 | From | Thierry Reding <> | Subject | Re: [PATCH v4 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path |
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On Tue, Mar 02, 2021 at 03:24:58PM +0300, Dmitry Osipenko wrote: > The tegra_powergate_power_up() has a typo in the error code path where it > will try to disable clocks twice, fix it. In practice that error never > happens, so this is a minor correction. > > Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 > Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 > Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/soc/tegra/pmc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Thierry [unhandled content-type:application/pgp-signature] | |