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    SubjectRE: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
    Date
    > > Hi Marc,
    > >
    > > Thanks for the patch.
    > >
    > > > Subject: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
    > > >
    > > > In anticipation of the removal of the msi_controller structure,
    > > > convert the ancient xilinx host controller driver to MSI domains.
    > > >
    > > > We end-up with the usual two domain structure, the top one being a
    > > > generic PCI/MSI domain, the bottom one being xilinx-specific and
    > > > handling the actual HW interrupt allocation.
    > > >
    > > > This allows us to fix some of the most appalling MSI programming,
    > > > where the message programmed in the device is the virtual IRQ number
    > > > instead of the allocated vector number. The allocator is also made
    > > > safe with a mutex. This should allow support for MultiMSI, but I
    > > > decided not to even try, since I cannot test it.
    > > >
    > > > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
    > > > Signed-off-by: Marc Zyngier <maz@kernel.org>
    > > > ---
    > > > drivers/pci/controller/Kconfig | 2 +-
    > > > drivers/pci/controller/pcie-xilinx.c | 234
    > > > +++++++++++----------------
    > > > 2 files changed, 97 insertions(+), 139 deletions(-)
    > > >
    > > > diff --git a/drivers/pci/controller/Kconfig
    > > > b/drivers/pci/controller/Kconfig index 5cc07d28a3a0..60045f7aafc5
    > > > 100644
    > > ...
    > >
    > >
    > > > +static struct irq_chip xilinx_msi_bottom_chip = {
    > > > + .name = "Xilinx MSI",
    > > > + .irq_set_affinity = xilinx_msi_set_affinity,
    > > > + .irq_compose_msi_msg = xilinx_compose_msi_msg,
    > > > +};
    > > >
    > > I see a crash while testing MSI in handle_edge_irq [<c015bdd4>]
    > > (handle_edge_irq) from [<c0157164>] (generic_handle_irq+0x28/0x38)
    > > [<c0157164>] (generic_handle_irq) from [<c03a9714>]
    > > (xilinx_pcie_intr_handler+0x17c/0x2b0)
    > > [<c03a9714>] (xilinx_pcie_intr_handler) from [<c0157d94>]
    > > (__handle_irq_event_percpu+0x3c/0xc0)
    > > [<c0157d94>] (__handle_irq_event_percpu) from [<c0157e44>]
    > > (handle_irq_event_percpu+0x2c/0x7c)
    > > [<c0157e44>] (handle_irq_event_percpu) from [<c0157ecc>]
    > > (handle_irq_event+0x38/0x5c) [<c0157ecc>] (handle_irq_event) from
    > > [<c015bc8c>] (handle_fasteoi_irq+0x9c/0x114)
    >
    > Thanks for that. Can you please try the following patch and let me know if it
    > helps?
    >
    > Thanks,
    >
    > M.
    >
    > diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-
    > xilinx.c
    > index ad9abf405167..14001febf59a 100644
    > --- a/drivers/pci/controller/pcie-xilinx.c
    > +++ b/drivers/pci/controller/pcie-xilinx.c
    > @@ -194,8 +194,18 @@ static struct pci_ops xilinx_pcie_ops = {
    >
    > /* MSI functions */
    >
    > +static void xilinx_msi_top_irq_ack(struct irq_data *d) {
    > + /*
    > + * xilinx_pcie_intr_handler() will have performed the Ack.
    > + * Eventually, this should be fixed and the Ack be moved in
    > + * the respective callbacks for INTx and MSI.
    > + */
    > +}
    > +
    > static struct irq_chip xilinx_msi_top_chip = {
    > .name = "PCIe MSI",
    > + .irq_ack = xilinx_msi_top_irq_ack,
    > };
    >
    > static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask
    > *mask, bool force) @@ -206,7 +216,7 @@ static int
    > xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mas static
    > void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) {
    > struct xilinx_pcie_port *pcie = irq_data_get_irq_chip_data(data);
    > - phys_addr_t pa = virt_to_phys(pcie);
    > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);
    >
    > msg->address_lo = lower_32_bits(pa);
    > msg->address_hi = upper_32_bits(pa);
    > @@ -468,7 +478,7 @@ static int xilinx_pcie_init_irq_domain(struct
    > xilinx_pcie_port *port)
    >
    > /* Setup MSI */
    > if (IS_ENABLED(CONFIG_PCI_MSI)) {
    > - phys_addr_t pa = virt_to_phys(port);
    > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(port), SZ_4K);
    >
    > ret = xilinx_allocate_msi_domains(port);
    > if (ret)
    >
    Thanks Marc.
    With above patch now everything works fine, tested a Samsung NVMe SSD.
    tst~# lspci
    00:00.0 PCI bridge: Xilinx Corporation Device 0706
    01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller 172Xa/172Xb (rev 01)

    Regards,
    Bharat

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