Messages in this thread | | | Subject | Re: [PATCH] x86/apic: Rudimentary typo fixes | From | Randy Dunlap <> | Date | Wed, 24 Mar 2021 10:49:23 -0700 |
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On 3/24/21 6:41 AM, Bhaskar Chowdhury wrote: > > s/preferrable/preferable/ > s/serivced/serviced/ > s/distributon/distribution/ > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
> --- > arch/x86/kernel/apic/apic.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c > index bda4f2a36868..e26ee6e67f47 100644 > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -619,7 +619,7 @@ static void setup_APIC_timer(void) > > if (this_cpu_has(X86_FEATURE_ARAT)) { > lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; > - /* Make LAPIC timer preferrable over percpu HPET */ > + /* Make LAPIC timer preferable over percpu HPET */ > lapic_clockevent.rating = 150; > } > > @@ -1532,7 +1532,7 @@ static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) > * Most probably by now the CPU has serviced that pending interrupt and it > * might not have done the ack_APIC_irq() because it thought, interrupt > * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear > - * the ISR bit and cpu thinks it has already serivced the interrupt. Hence > + * the ISR bit and cpu thinks it has already serviced the interrupt. Hence > * a vector might get locked. It was noticed for timer irq (vector > * 0x31). Issue an extra EOI to clear ISR. > * > @@ -1657,7 +1657,7 @@ static void setup_local_APIC(void) > */ > /* > * Actually disabling the focus CPU check just makes the hang less > - * frequent as it makes the interrupt distributon model be more > + * frequent as it makes the interrupt distribution model be more > * like LRU than MRU (the short-term load is more even across CPUs). > */ > > --
-- ~Randy
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