lkml.org 
[lkml]   [2021]   [Mar]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v3 02/41] powerpc/40x: Don't use SPRN_SPRG_SCRATCH0/1 in TLB miss handlers
    Date
    SPRN_SPRG_SCRATCH5 is used to save SPRN_PID.
    SPRN_SPRG_SCRATCH6 is already available.

    SPRN_PID is only 8 bits. We have r12 that contains CR.
    We only need to preserve CR0, so we have space available in r12
    to save PID.

    Keep PID in r12 and free up SPRN_SPRG_SCRATCH5.

    Then In TLB miss handlers, instead of using SPRN_SPRG_SCRATCH0 and
    SPRN_SPRG_SCRATCH1, use SPRN_SPRG_SCRATCH5 and SPRN_SPRG_SCRATCH6
    to avoid future conflicts with normal exception prologs.

    Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
    ---
    arch/powerpc/kernel/head_40x.S | 39 ++++++++++++++++------------------
    1 file changed, 18 insertions(+), 21 deletions(-)

    diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
    index 24724a7dad49..383238a98f77 100644
    --- a/arch/powerpc/kernel/head_40x.S
    +++ b/arch/powerpc/kernel/head_40x.S
    @@ -249,13 +249,13 @@ _ENTRY(saved_ksp_limit)
    * load TLB entries from the page table if they exist.
    */
    START_EXCEPTION(0x1100, DTLBMiss)
    - mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
    - mtspr SPRN_SPRG_SCRATCH1, r11
    + mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
    + mtspr SPRN_SPRG_SCRATCH6, r11
    mtspr SPRN_SPRG_SCRATCH3, r12
    mtspr SPRN_SPRG_SCRATCH4, r9
    mfcr r12
    mfspr r9, SPRN_PID
    - mtspr SPRN_SPRG_SCRATCH5, r9
    + rlwimi r12, r9, 0, 0xff
    mfspr r10, SPRN_DEAR /* Get faulting address */

    /* If we are faulting a kernel address, we have to use the
    @@ -316,13 +316,12 @@ _ENTRY(saved_ksp_limit)
    /* The bailout. Restore registers to pre-exception conditions
    * and call the heavyweights to help us out.
    */
    - mfspr r9, SPRN_SPRG_SCRATCH5
    - mtspr SPRN_PID, r9
    - mtcr r12
    + mtspr SPRN_PID, r12
    + mtcrf 0x80, r12
    mfspr r9, SPRN_SPRG_SCRATCH4
    mfspr r12, SPRN_SPRG_SCRATCH3
    - mfspr r11, SPRN_SPRG_SCRATCH1
    - mfspr r10, SPRN_SPRG_SCRATCH0
    + mfspr r11, SPRN_SPRG_SCRATCH6
    + mfspr r10, SPRN_SPRG_SCRATCH5
    b DataStorage

    /* 0x1200 - Instruction TLB Miss Exception
    @@ -330,13 +329,13 @@ _ENTRY(saved_ksp_limit)
    * registers and bailout to a different point.
    */
    START_EXCEPTION(0x1200, ITLBMiss)
    - mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
    - mtspr SPRN_SPRG_SCRATCH1, r11
    + mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
    + mtspr SPRN_SPRG_SCRATCH6, r11
    mtspr SPRN_SPRG_SCRATCH3, r12
    mtspr SPRN_SPRG_SCRATCH4, r9
    mfcr r12
    mfspr r9, SPRN_PID
    - mtspr SPRN_SPRG_SCRATCH5, r9
    + rlwimi r12, r9, 0, 0xff
    mfspr r10, SPRN_SRR0 /* Get faulting address */

    /* If we are faulting a kernel address, we have to use the
    @@ -397,13 +396,12 @@ _ENTRY(saved_ksp_limit)
    /* The bailout. Restore registers to pre-exception conditions
    * and call the heavyweights to help us out.
    */
    - mfspr r9, SPRN_SPRG_SCRATCH5
    - mtspr SPRN_PID, r9
    - mtcr r12
    + mtspr SPRN_PID, r12
    + mtcrf 0x80, r12
    mfspr r9, SPRN_SPRG_SCRATCH4
    mfspr r12, SPRN_SPRG_SCRATCH3
    - mfspr r11, SPRN_SPRG_SCRATCH1
    - mfspr r10, SPRN_SPRG_SCRATCH0
    + mfspr r11, SPRN_SPRG_SCRATCH6
    + mfspr r10, SPRN_SPRG_SCRATCH5
    b InstructionAccess

    EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
    @@ -543,13 +541,12 @@ finish_tlb_load:

    /* Done...restore registers and get out of here.
    */
    - mfspr r9, SPRN_SPRG_SCRATCH5
    - mtspr SPRN_PID, r9
    - mtcr r12
    + mtspr SPRN_PID, r12
    + mtcrf 0x80, r12
    mfspr r9, SPRN_SPRG_SCRATCH4
    mfspr r12, SPRN_SPRG_SCRATCH3
    - mfspr r11, SPRN_SPRG_SCRATCH1
    - mfspr r10, SPRN_SPRG_SCRATCH0
    + mfspr r11, SPRN_SPRG_SCRATCH6
    + mfspr r10, SPRN_SPRG_SCRATCH5
    rfi /* Should sync shadow TLBs */
    b . /* prevent prefetch past rfi */

    --
    2.25.0
    \
     
     \ /
      Last update: 2021-03-12 13:51    [W:4.176 / U:0.020 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site