Messages in this thread | | | From | Daniel Palmer <> | Date | Fri, 12 Mar 2021 19:35:38 +0900 | Subject | Re: [PATCH v2] irqchip/irq-mst: Support polarity configuration |
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On Fri, 12 Mar 2021 at 01:11, Mark-PK Tsai <mark-pk.tsai@mediatek.com> wrote: > Why irq could accept either?
As the irq intc has no way to clear it's triggered state (no eoi) it must just pass the signal through instead of latching it? Otherwise it would latch once and never again right? That's what I really didn't understand. If it just passes the signal through and maybe inverts it then the GIC can use edge or level I think.
> So maybe we don't need to do extra work to check the type for an fiq or irq controller?
I think without the eoi callback for the fiq it would only ever fire once. I don't think doing the same eoi callback for the irq intc hurts anything but it wouldn't do anything either from what I can tell.
> And I will update the patch as following:
I think maybe Marc or someone else that knows better than I do should comment on what needs to happen. My input is just that the fiq controller seems to trigger on an edge, holds it's signal to the GIC high until eoi happens and then only triggers again on an edge. I guess it doesn't matter if it's an edge or level if that's how it works but you'd only get one interrupt out of it per edge even if configured as a level interrupt.
The main thing I didn't want was filtering out edge interrupts entirely as that breaks using edge interrupts with gpios i.e. using gpiomon. With the changes to set the polarity it can now detect rising or falling edge gpio events. :)
Thanks,
Daniel
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