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Subject[PATCH v3 3/6] dt-bindings: power: tegra: Add binding for core power domain
Date
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Add binding for the core power domain.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../power/nvidia,tegra20-core-domain.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml

diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
new file mode 100644
index 000000000000..bc68c5757d45
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Core Power Domain
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+allOf:
+ - $ref: power-domain.yaml#
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-core-domain
+ - nvidia,tegra30-core-domain
+
+ operating-points-v2:
+ description:
+ Should contain level, voltages and opp-supported-hw property.
+ The supported-hw is a bitfield indicating SoC speedo or process
+ ID mask.
+
+ "#power-domain-cells":
+ const: 0
+
+ power-supply:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to voltage regulator connected to the SoC Core power rail.
+
+required:
+ - compatible
+ - operating-points-v2
+ - "#power-domain-cells"
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ power-domain {
+ compatible = "nvidia,tegra20-core-domain";
+ operating-points-v2 = <&opp_table>;
+ power-supply = <&regulator>;
+ #power-domain-cells = <0>;
+ };
--
2.29.2
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