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    Subject[PATCH 5.11 692/775] coresight: etm4x: Handle accesses to TRCSTALLCTLR
    Date
    From: Suzuki K Poulose <suzuki.poulose@arm.com>

    commit f72896063396b0cb205cbf0fd76ec6ab3ca11c8a upstream.

    TRCSTALLCTLR register is only implemented if

    TRCIDR3.STALLCTL == 0b1

    Make sure the driver touches the register only it is implemented.

    Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com
    Cc: stable@vger.kernel.org
    Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
    Cc: Mike Leach <mike.leach@linaro.org>
    Cc: Leo Yan <leo.yan@linaro.org>
    Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
    Link: https://lore.kernel.org/r/20210201181351.1475223-32-mathieu.poirier@linaro.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
    drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
    2 files changed, 7 insertions(+), 4 deletions(-)

    --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
    +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
    @@ -226,7 +226,8 @@ static int etm4_enable_hw(struct etmv4_d
    writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
    writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
    writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
    - writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
    + if (drvdata->stallctl)
    + writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
    writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
    writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
    writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
    @@ -1288,7 +1289,8 @@ static int etm4_cpu_save(struct etmv4_dr
    state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
    state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
    state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
    - state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
    + if (drvdata->stallctl)
    + state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
    state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
    state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
    state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
    @@ -1398,7 +1400,8 @@ static void etm4_cpu_restore(struct etmv
    writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
    writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
    writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
    - writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
    + if (drvdata->stallctl)
    + writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
    writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
    writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
    writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
    --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
    +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
    @@ -389,7 +389,7 @@ static ssize_t mode_store(struct device
    config->eventctrl1 &= ~BIT(12);

    /* bit[8], Instruction stall bit */
    - if (config->mode & ETM_MODE_ISTALL_EN)
    + if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
    config->stall_ctrl |= BIT(8);
    else
    config->stall_ctrl &= ~BIT(8);

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