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    Subject[PATCH 5.11 604/775] MIPS: Support binutils configured with --enable-mips-fix-loongson3-llsc=yes
    Date
    From: Aurelien Jarno <aurelien@aurel32.net>

    commit 5373ae67c3aad1ab306cc722b5a80b831eb4d4d1 upstream.

    >From version 2.35, binutils can be configured with
    --enable-mips-fix-loongson3-llsc=yes, which means it defaults to
    -mfix-loongson3-llsc. This breaks labels which might then point at the
    wrong instruction.

    The workaround to explicitly pass -mno-fix-loongson3-llsc has been
    added in Linux version 5.1, but is only enabled when building a Loongson
    64 kernel. As vendors might use a common toolchain for building Loongson
    and non-Loongson kernels, just move that workaround to
    arch/mips/Makefile. At the same time update the comments to reflect the
    current status.

    Cc: stable@vger.kernel.org # 5.1+
    Cc: YunQiang Su <syq@debian.org>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/mips/Makefile | 19 +++++++++++++++++++
    arch/mips/loongson64/Platform | 22 ----------------------
    2 files changed, 19 insertions(+), 22 deletions(-)

    --- a/arch/mips/Makefile
    +++ b/arch/mips/Makefile
    @@ -136,6 +136,25 @@ cflags-$(CONFIG_SB1XXX_CORELIS) += $(cal
    #
    cflags-y += -fno-stack-check

    +# binutils from v2.35 when built with --enable-mips-fix-loongson3-llsc=yes,
    +# supports an -mfix-loongson3-llsc flag which emits a sync prior to each ll
    +# instruction to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h
    +# for a description).
    +#
    +# We disable this in order to prevent the assembler meddling with the
    +# instruction that labels refer to, ie. if we label an ll instruction:
    +#
    +# 1: ll v0, 0(a0)
    +#
    +# ...then with the assembler fix applied the label may actually point at a sync
    +# instruction inserted by the assembler, and if we were using the label in an
    +# exception table the table would no longer contain the address of the ll
    +# instruction.
    +#
    +# Avoid this by explicitly disabling that assembler behaviour.
    +#
    +cflags-y += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
    +
    #
    # CPU-dependent compiler/assembler options for optimization.
    #
    --- a/arch/mips/loongson64/Platform
    +++ b/arch/mips/loongson64/Platform
    @@ -6,28 +6,6 @@
    cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap

    #
    -# Some versions of binutils, not currently mainline as of 2019/02/04, support
    -# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
    -# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
    -# description).
    -#
    -# We disable this in order to prevent the assembler meddling with the
    -# instruction that labels refer to, ie. if we label an ll instruction:
    -#
    -# 1: ll v0, 0(a0)
    -#
    -# ...then with the assembler fix applied the label may actually point at a sync
    -# instruction inserted by the assembler, and if we were using the label in an
    -# exception table the table would no longer contain the address of the ll
    -# instruction.
    -#
    -# Avoid this by explicitly disabling that assembler behaviour. If upstream
    -# binutils does not merge support for the flag then we can revisit & remove
    -# this later - for now it ensures vendor toolchains don't cause problems.
    -#
    -cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
    -
    -#
    # binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
    # as MIPS64 R2; older versions as just R1. This leaves the possibility open
    # that GCC might generate R2 code for -march=loongson3a which then is rejected

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