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    Subject[PATCH 4.19 124/247] clk: sunxi-ng: h6: Fix clock divider range on some clocks
    Date
    From: Andre Przywara <andre.przywara@arm.com>

    [ Upstream commit 04ef679591c76571a9e7d5ca48316cc86fa0ef12 ]

    While comparing clocks between the H6 and H616, some of the M factor
    ranges were found to be wrong: the manual says they are only covering
    two bits [1:0], but our code had "5" in the number-of-bits field.

    By writing 0xff into that register in U-Boot and via FEL, it could be
    confirmed that bits [4:2] are indeed masked off, so the manual is right.

    Change to number of bits in the affected clock's description.

    Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
    Signed-off-by: Andre Przywara <andre.przywara@arm.com>
    Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@arm.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++----
    1 file changed, 4 insertions(+), 4 deletions(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
    index 3449dcf1908ef..1197ace591247 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
    @@ -223,7 +223,7 @@ static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
    static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
    psi_ahb1_ahb2_parents,
    0x510,
    - 0, 5, /* M */
    + 0, 2, /* M */
    8, 2, /* P */
    24, 2, /* mux */
    0);
    @@ -232,19 +232,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
    "psi-ahb1-ahb2",
    "pll-periph0" };
    static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
    - 0, 5, /* M */
    + 0, 2, /* M */
    8, 2, /* P */
    24, 2, /* mux */
    0);

    static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
    - 0, 5, /* M */
    + 0, 2, /* M */
    8, 2, /* P */
    24, 2, /* mux */
    0);

    static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
    - 0, 5, /* M */
    + 0, 2, /* M */
    8, 2, /* P */
    24, 2, /* mux */
    0);
    --
    2.27.0


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