Messages in this thread | | | Subject | Re: [PATCH v2 06/11] clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs | From | Stephen Boyd <> | Date | Mon, 08 Feb 2021 10:19:53 -0800 |
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Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:54) > All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs > and not generic alphas: this was producing bad effects over the entire > clock tree of MSM8998, where any GPLL child clock was declaring a false > clock rate, due to their parent also showing the same. > > The issue resides in the calculation of the clock rate for the specific > Alpha PLL type, where Fabia has a different register layout; switching > the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate > (calculation) reading. While at it, also make these PLLs fixed since > their rate is supposed to *never* be changed while the system runs, as > this would surely crash the entire SoC. > > Now all the children of all the PLLs are also complying with their > specified clock table and system stability is improved. > > Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > ---
Applied to clk-next
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