Messages in this thread | | | Subject | Re: [PATCH 1/3] MIPS: kernel: Support extracting off-line stack traces from user-space with perf | From | Tiezhu Yang <> | Date | Wed, 3 Feb 2021 21:12:28 +0800 |
| |
On 2/3/21 6:40 PM, Thomas Bogendoerfer wrote: > On Mon, Feb 01, 2021 at 08:56:06PM +0800, Tiezhu Yang wrote: >> On 02/01/2021 06:43 PM, Thomas Bogendoerfer wrote: >>> On Tue, Dec 29, 2020 at 08:55:59PM +0800, Tiezhu Yang wrote: >>>> +++ b/arch/mips/include/uapi/asm/perf_regs.h >>>> @@ -0,0 +1,42 @@ >>>> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ >>>> +#ifndef _ASM_MIPS_PERF_REGS_H >>>> +#define _ASM_MIPS_PERF_REGS_H >>>> + >>>> +enum perf_event_mips_regs { >>>> + PERF_REG_MIPS_PC, >>>> + PERF_REG_MIPS_R1, >>>> + PERF_REG_MIPS_R2, >>>> + PERF_REG_MIPS_R3, >>>> + PERF_REG_MIPS_R4, >>>> + PERF_REG_MIPS_R5, >>>> + PERF_REG_MIPS_R6, >>>> + PERF_REG_MIPS_R7, >>>> + PERF_REG_MIPS_R8, >>>> + PERF_REG_MIPS_R9, >>>> + PERF_REG_MIPS_R10, >>>> + PERF_REG_MIPS_R11, >>>> + PERF_REG_MIPS_R12, >>>> + PERF_REG_MIPS_R13, >>>> + PERF_REG_MIPS_R14, >>>> + PERF_REG_MIPS_R15, >>>> + PERF_REG_MIPS_R16, >>>> + PERF_REG_MIPS_R17, >>>> + PERF_REG_MIPS_R18, >>>> + PERF_REG_MIPS_R19, >>>> + PERF_REG_MIPS_R20, >>>> + PERF_REG_MIPS_R21, >>>> + PERF_REG_MIPS_R22, >>>> + PERF_REG_MIPS_R23, >>>> + PERF_REG_MIPS_R24, >>>> + PERF_REG_MIPS_R25, >>>> + /* >>>> + * 26 and 27 are k0 and k1, they are always clobbered thus not >>>> + * stored. >>>> + */ >>> haveing this hole here make all code more complicated. Does it hurt >>> to have R26 and R27 in the list ? >> I think there is no effect if have R26 and R27 in the list. >> >> In the perf_reg_value(), PERF_REG_MIPS_R{26,27} are default case. > why make them special ? After all they are real registers and are only > defined special by current ABIs.
By convention, $26 and $27 are k registers which are reserved for use by the OS kernel.
Here is an explanation [1]:
"An interrupt handler must save any general - purpose registers that it is going to use (to be restored at return). But to do so requires you to modify at least one register first (something like sw $t0, saved_t0 expands to two machine instructions using $at).
This situation is resolved by forbidding user programs from using two general - purpose registers, $k0 and $k1 (The k stands for kernel, which an exception handler is part of). The interrupt handler is allowed to use $k0 and $k1 without having to save or restore their values. This allows just enough leeway to start saving registers, as well as making returning from the interrupt handler possible."
[1] https://stackoverflow.com/questions/27922315/how-to-use-mips-k0-and-k1-registers
> >> Should I modify enum perf_event_mips_regs to add R26 and R27, >> and then send v2? > yes please. > > Thomas. >
| |