Messages in this thread | | | Subject | Re: [PATCH] [perf] powerpc: Remove unsupported metrics | From | kajoljain <> | Date | Fri, 26 Feb 2021 11:03:11 +0530 |
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On 2/24/21 11:44 PM, Paul A. Clarke wrote: > Several metrics are defined based on unsupported / non-existent > events, and silently discarded. Remove them for good code hygiene > and to avoid confusion. >
Hi Paul, Thanks for the patch. Changes looks good to me.
Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
Thanks, Kajol Jain
> Signed-off-by: Paul A. Clarke <pc@us.ibm.com> > --- > .../arch/powerpc/power9/metrics.json | 132 ------------------ > 1 file changed, 132 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/powerpc/power9/metrics.json b/tools/perf/pmu-events/arch/powerpc/power9/metrics.json > index f8784c608479..140402d2855f 100644 > --- a/tools/perf/pmu-events/arch/powerpc/power9/metrics.json > +++ b/tools/perf/pmu-events/arch/powerpc/power9/metrics.json > @@ -1209,156 +1209,24 @@ > "MetricGroup": "instruction_stats_percent_per_ref", > "MetricName": "inst_from_rmem_percent" > }, > - { > - "BriefDescription": "%L2 Modified CO Cache read Utilization (4 pclks per disp attempt)", > - "MetricExpr": "((PM_L2_CASTOUT_MOD/2)*4)/ PM_RUN_CYC * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_co_m_rd_util" > - }, > - { > - "BriefDescription": "L2 dcache invalidates per run inst (per core)", > - "MetricExpr": "(PM_L2_DC_INV / 2) / PM_RUN_INST_CMPL * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_dc_inv_rate_percent" > - }, > { > "BriefDescription": "Demand load misses as a % of L2 LD dispatches (per thread)", > "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID / (PM_L2_LD / 2) * 100", > "MetricGroup": "l2_stats", > "MetricName": "l2_dem_ld_disp_percent" > }, > - { > - "BriefDescription": "L2 Icache invalidates per run inst (per core)", > - "MetricExpr": "(PM_L2_IC_INV / 2) / PM_RUN_INST_CMPL * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ic_inv_rate_percent" > - }, > - { > - "BriefDescription": "L2 Inst misses as a % of total L2 Inst dispatches (per thread)", > - "MetricExpr": "PM_L2_INST_MISS / PM_L2_INST * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_inst_miss_ratio_percent" > - }, > - { > - "BriefDescription": "Average number of cycles between L2 Load hits", > - "MetricExpr": "(PM_L2_LD_HIT / PM_RUN_CYC) / 2", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ld_hit_frequency" > - }, > - { > - "BriefDescription": "Average number of cycles between L2 Load misses", > - "MetricExpr": "(PM_L2_LD_MISS / PM_RUN_CYC) / 2", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ld_miss_frequency" > - }, > - { > - "BriefDescription": "L2 Load misses as a % of total L2 Load dispatches (per thread)", > - "MetricExpr": "PM_L2_LD_MISS / PM_L2_LD * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ld_miss_ratio_percent" > - }, > - { > - "BriefDescription": "% L2 load disp attempts Cache read Utilization (4 pclks per disp attempt)", > - "MetricExpr": "((PM_L2_RCLD_DISP/2)*4)/ PM_RUN_CYC * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ld_rd_util" > - }, > - { > - "BriefDescription": "L2 load misses that require a cache write (4 pclks per disp attempt) % of pclks", > - "MetricExpr": "((( PM_L2_LD_DISP - PM_L2_LD_HIT)/2)*4)/ PM_RUN_CYC * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_ldmiss_wr_util" > - }, > - { > - "BriefDescription": "L2 local pump prediction success", > - "MetricExpr": "PM_L2_LOC_GUESS_CORRECT / (PM_L2_LOC_GUESS_CORRECT + PM_L2_LOC_GUESS_WRONG) * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_local_pred_correct_percent" > - }, > - { > - "BriefDescription": "L2 COs that were in M,Me,Mu state as a % of all L2 COs", > - "MetricExpr": "PM_L2_CASTOUT_MOD / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_mod_co_percent" > - }, > - { > - "BriefDescription": "% of L2 Load RC dispatch atampts that failed because of address collisions and cclass conflicts", > - "MetricExpr": "(PM_L2_RCLD_DISP_FAIL_ADDR )/ PM_L2_RCLD_DISP * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_rc_ld_disp_addr_fail_percent" > - }, > - { > - "BriefDescription": "% of L2 Load RC dispatch attempts that failed", > - "MetricExpr": "(PM_L2_RCLD_DISP_FAIL_ADDR + PM_L2_RCLD_DISP_FAIL_OTHER)/ PM_L2_RCLD_DISP * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_rc_ld_disp_fail_percent" > - }, > - { > - "BriefDescription": "% of L2 Store RC dispatch atampts that failed because of address collisions and cclass conflicts", > - "MetricExpr": "PM_L2_RCST_DISP_FAIL_ADDR / PM_L2_RCST_DISP * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_rc_st_disp_addr_fail_percent" > - }, > - { > - "BriefDescription": "% of L2 Store RC dispatch attempts that failed", > - "MetricExpr": "(PM_L2_RCST_DISP_FAIL_ADDR + PM_L2_RCST_DISP_FAIL_OTHER)/ PM_L2_RCST_DISP * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_rc_st_disp_fail_percent" > - }, > - { > - "BriefDescription": "L2 Cache Read Utilization (per core)", > - "MetricExpr": "(((PM_L2_RCLD_DISP/2)*4)/ PM_RUN_CYC * 100) + (((PM_L2_RCST_DISP/2)*4)/PM_RUN_CYC * 100) + (((PM_L2_CASTOUT_MOD/2)*4)/PM_RUN_CYC * 100)", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_rd_util_percent" > - }, > - { > - "BriefDescription": "L2 COs that were in T,Te,Si,S state as a % of all L2 COs", > - "MetricExpr": "PM_L2_CASTOUT_SHR / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_shr_co_percent" > - }, > { > "BriefDescription": "L2 Store misses as a % of total L2 Store dispatches (per thread)", > "MetricExpr": "PM_L2_ST_MISS / PM_L2_ST * 100", > "MetricGroup": "l2_stats", > "MetricName": "l2_st_miss_ratio_percent" > }, > - { > - "BriefDescription": "% L2 store disp attempts Cache read Utilization (4 pclks per disp attempt)", > - "MetricExpr": "((PM_L2_RCST_DISP/2)*4) / PM_RUN_CYC * 100", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_st_rd_util" > - }, > { > "BriefDescription": "L2 stores that require a cache write (4 pclks per disp attempt) % of pclks", > "MetricExpr": "((PM_L2_ST_DISP/2)*4) / PM_RUN_CYC * 100", > "MetricGroup": "l2_stats", > "MetricName": "l2_st_wr_util" > }, > - { > - "BriefDescription": "L2 Cache Write Utilization (per core)", > - "MetricExpr": "((((PM_L2_LD_DISP - PM_L2_LD_HIT)/2)*4) / PM_RUN_CYC * 100) + (((PM_L2_ST_DISP/2)*4) / PM_RUN_CYC * 100)", > - "MetricGroup": "l2_stats", > - "MetricName": "l2_wr_util_percent" > - }, > - { > - "BriefDescription": "Average number of cycles between L3 Load hits", > - "MetricExpr": "(PM_L3_LD_HIT / PM_RUN_CYC) / 2", > - "MetricGroup": "l3_stats", > - "MetricName": "l3_ld_hit_frequency" > - }, > - { > - "BriefDescription": "Average number of cycles between L3 Load misses", > - "MetricExpr": "(PM_L3_LD_MISS / PM_RUN_CYC) / 2", > - "MetricGroup": "l3_stats", > - "MetricName": "l3_ld_miss_frequency" > - }, > - { > - "BriefDescription": "Average number of Write-in machines used. 1 of 8 WI machines is sampled every L3 cycle", > - "MetricExpr": "(PM_L3_WI_USAGE / PM_RUN_CYC) * 8", > - "MetricGroup": "l3_stats", > - "MetricName": "l3_wi_usage" > - }, > { > "BriefDescription": "Average icache miss latency", > "MetricExpr": "PM_IC_DEMAND_CYC / PM_IC_DEMAND_REQ", >
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