Messages in this thread | | | Date | Thu, 18 Feb 2021 08:58:35 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output |
| |
Hi,
On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote: > Previously the variable rate audio pll output was fixed to a divider of > four. This is unfortunately incompatible with generating commonly used > I2S core clock rates like 24.576MHz from the 24MHz parent clock. > This commit adds support for arbitrary audio pll output dividers to fix > that. > > Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
It's not really clear to me how that would help.
The closest frequency we can provide for 24.576MHz would be 24580645 Hz, with N = 127, M = 31 and P = 4, so it would work with what we have already?
Maxime [unhandled content-type:application/pgp-signature] | |