Messages in this thread Patch in this message | | | Subject | Re: [PATCH] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers | From | Like Xu <> | Date | Thu, 18 Feb 2021 10:31:26 +0800 |
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Hi Peter,
Would you help pick up this patch so that we can enable guest Arch LBR?
--- thx,likexu
On 2021/2/3 15:03, Like Xu wrote: > If the platform supports LBR_INFO register, the x86_pmu.lbr_info will > be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO > in the x86_perf_get_lbr() directly, instead of relying on lbr_format check. > > Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x > to hold metadata for the operation, including mispredict, TSX, and > elapsed cycle time information. > > Cc: Kan Liang <kan.liang@linux.intel.com> > Cc: Peter Zijlstra (Intel) <peterz@infradead.org> > Signed-off-by: Like Xu <like.xu@linux.intel.com> > --- > arch/x86/events/intel/lbr.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c > index 21890dacfcfe..355ea70f1879 100644 > --- a/arch/x86/events/intel/lbr.c > +++ b/arch/x86/events/intel/lbr.c > @@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void) > */ > int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) > { > - int lbr_fmt = x86_pmu.intel_cap.lbr_format; > - > lbr->nr = x86_pmu.lbr_nr; > lbr->from = x86_pmu.lbr_from; > lbr->to = x86_pmu.lbr_to; > - lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; > + lbr->info = x86_pmu.lbr_info; > > return 0; > } >
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