Messages in this thread Patch in this message | | | From | Sai Prakash Ranjan <> | Subject | [PATCH 2/3] arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity | Date | Tue, 16 Feb 2021 15:17:48 +0530 |
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As per interrupt documentation for SM8350 SoC, the polarity for level triggered PMU interrupt is low, fix this.
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5ef460458f5c..e8bf3f95c674 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -153,7 +153,7 @@ memory@80000000 { pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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