Messages in this thread | | | From | Andy Shevchenko <> | Date | Mon, 15 Feb 2021 14:53:46 +0200 | Subject | Re: [PATCH v2] gpio: pca953x: add support for open drain pins on PCAL6524 |
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Hint: don't forget to include reviewers from previous version
On Thu, Feb 11, 2021 at 7:52 PM Alban Bedel <alban.bedel@aerq.com> wrote: > > From a quick glance at various datasheets the PCAL6524 and the > PCAL6534 seems to be the only chips in this family that support > setting the drive mode of single pins. Other chips either don't > support it at all, or can only set the drive mode of whole banks, > which doesn't map to the GPIO API. > > Add a new flag, PCAL65xx_REGS, to mark chips that have the extra > registers needed for this feature. Then mark the needed register banks > as readable and writable, here we don't set OUT_CONF as writable, > although it is, as we only need to read it. Finally add a function > that configures the OUT_INDCONF register when the GPIO API sets the > drive mode of the pins.
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> +#define PCAL65xx_REGS BIT(10)
Can we have it as a _TYPE, please?
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> +#define PCAL65xx_BANK_INDOUT_CONF BIT(8 + 12)
IND is a bit ambiguous based on the description below. After you elaborate, I probably can propose better naming.
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> + * - PCAL65xx with individual pin configuration > + * Individual pin output config 0x40 + 12 * bank_size RW
Not sure I understand what "individual" means here (no, I haven't looked into the datasheet).
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> + if (config == PIN_CONFIG_DRIVE_OPEN_DRAIN) > + val = mask; > + else if (config == PIN_CONFIG_DRIVE_PUSH_PULL) > + val = 0; > + else > + return -EINVAL;
Switch-case will look more naturally here (despite being longer in terms of LOCs).
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> +exit:
exit_unlock:
> + mutex_unlock(&chip->i2c_lock); > + return ret;
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> +#define OF_L65XX(__nrgpio) OF_953X(__nrgpio, PCA_LATCH_INT | PCAL65xx_REGS)
When you change to the type, it will go accordingly. Don't add LATCH_INT to the macro.
-- With Best Regards, Andy Shevchenko
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