Messages in this thread | | | Subject | Re: [PATCH v1 2/2] clk: qcom: Add Global Clock controller (GCC) driver for SC7280 | From | Taniya Das <> | Date | Wed, 10 Feb 2021 23:54:02 +0530 |
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Thanks Stephen for your review comments.
On 1/13/2021 1:34 AM, Stephen Boyd wrote:
>> + >> +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { >> + .cmd_rcgr = 0x7500c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_8, >> + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gcc_sdcc1_apps_clk_src", >> + .parent_data = gcc_parent_data_8, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_8), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > This needs to use floor clk ops? >
My bad I missed them in my patch, latest patch has this fixed.
>> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), >> + F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { >> + .cmd_rcgr = 0x7502c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gcc_sdcc1_ice_core_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > Same. > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { >> + F(400000, P_BI_TCXO, 12, 1, 4), >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { >> + .cmd_rcgr = 0x1400c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_9, >> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gcc_sdcc2_apps_clk_src", >> + .parent_data = gcc_parent_data_9, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_9), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > Same. > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { >> + F(400000, P_BI_TCXO, 12, 1, 4), >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { >> + .cmd_rcgr = 0x1600c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gcc_sdcc4_apps_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > Same. > >> + }, >> +}; >> + > [...] >> +static struct clk_branch gcc_cpuss_ahb_clk = { >> + .halt_reg = 0x48000, >> + .halt_check = BRANCH_HALT_VOTED, >> + .hwcg_reg = 0x48000, >> + .hwcg_bit = 1, >> + .clkr = { >> + .enable_reg = 0x52000, >> + .enable_mask = BIT(21), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_cpuss_ahb_clk", >> + .parent_data = &(const struct clk_parent_data){ >> + .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, >> + }, >> + .num_parents = 1, >> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, > > Why is it critical? Please add a comment like sc7180. >
Updated the comment in the latest patch.
>> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> +
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