Messages in this thread Patch in this message | | | From | Jonathan Neuschäfer <> | Subject | [PATCH v2 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node | Date | Tue, 7 Dec 2021 22:08:18 +0100 |
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The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs that expose misc functionality such as chip model and version information or pinmux settings.
This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for enabling pinctrl on this SoC.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
--- v2: - Rename node to syscon@b0000000
v1: - https://lore.kernel.org/lkml/20210602120329.2444672-4-j.neuschaefer@gmx.net/ --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb1874840..a17ee70085dd0 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -33,6 +33,11 @@ soc { interrupt-parent = <&aic>; ranges;
+ gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; -- 2.30.2
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