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SubjectRe: [PATCH v4 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings
On Mon, 6 Dec 2021 at 17:32, David Virag <virag.david003@gmail.com> wrote:
>
> Provide dt-schema documentation for Exynos7885 SoC clock controller.
> Description is modified from Exynos850 clock controller documentation as
> I couldn't describe it any better, that was written by Sam Protsenko.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

> Changes in v2:
> - Fixed double : in description
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Fix leading 0x in example.
>
> .../clock/samsung,exynos7885-clock.yaml | 166 ++++++++++++++++++
> 1 file changed, 166 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
> new file mode 100644
> index 000000000000..7e5a9cac2fd2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos7885 SoC clock controller
> +
> +maintainers:
> + - Dávid Virág <virag.david003@gmail.com>
> + - Chanwoo Choi <cw00.choi@samsung.com>
> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> + - Sylwester Nawrocki <s.nawrocki@samsung.com>
> + - Tomasz Figa <tomasz.figa@gmail.com>
> +
> +description: |
> + Exynos7885 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. The root clock in that root tree
> + is an external clock: OSCCLK (26 MHz). This external clock must be defined
> + as a fixed-rate clock in dts.
> +
> + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'dt-bindings/clock/exynos7885.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynos7885-cmu-top
> + - samsung,exynos7885-cmu-core
> + - samsung,exynos7885-cmu-peri
> +
> + clocks:
> + minItems: 1
> + maxItems: 10
> +
> + clock-names:
> + minItems: 1
> + maxItems: 10
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-top
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-core
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_CORE bus clock (from CMU_TOP)
> + - description: CCI clock (from CMU_TOP)
> + - description: G3D clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_core_bus
> + - const: dout_core_cci
> + - const: dout_core_g3d
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-peri
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_PERI bus clock (from CMU_TOP)
> + - description: SPI0 clock (from CMU_TOP)
> + - description: SPI1 clock (from CMU_TOP)
> + - description: UART0 clock (from CMU_TOP)
> + - description: UART1 clock (from CMU_TOP)
> + - description: UART2 clock (from CMU_TOP)
> + - description: USI0 clock (from CMU_TOP)
> + - description: USI1 clock (from CMU_TOP)
> + - description: USI2 clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_peri_bus
> + - const: dout_peri_spi0
> + - const: dout_peri_spi1
> + - const: dout_peri_uart0
> + - const: dout_peri_uart1
> + - const: dout_peri_uart2
> + - const: dout_peri_usi0
> + - const: dout_peri_usi1
> + - const: dout_peri_usi2
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_PERI
> + - |
> + #include <dt-bindings/clock/exynos7885.h>
> +
> + cmu_peri: clock-controller@10010000 {
> + compatible = "samsung,exynos7885-cmu-peri";
> + reg = <0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_PERI_BUS>,
> + <&cmu_top CLK_DOUT_PERI_SPI0>,
> + <&cmu_top CLK_DOUT_PERI_SPI1>,
> + <&cmu_top CLK_DOUT_PERI_UART0>,
> + <&cmu_top CLK_DOUT_PERI_UART1>,
> + <&cmu_top CLK_DOUT_PERI_UART2>,
> + <&cmu_top CLK_DOUT_PERI_USI0>,
> + <&cmu_top CLK_DOUT_PERI_USI1>,
> + <&cmu_top CLK_DOUT_PERI_USI2>;
> + clock-names = "oscclk",
> + "dout_peri_bus",
> + "dout_peri_spi0",
> + "dout_peri_spi1",
> + "dout_peri_uart0",
> + "dout_peri_uart1",
> + "dout_peri_uart2",
> + "dout_peri_usi0",
> + "dout_peri_usi1",
> + "dout_peri_usi2";
> + };
> +
> +...
> --
> 2.34.1
>

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