Messages in this thread | | | From | Linus Walleij <> | Date | Sun, 5 Dec 2021 00:37:52 +0100 | Subject | Re: [PATCH 5/6] irq: spear-shirq: Add support for IRQ 0..6 |
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On Thu, Dec 2, 2021 at 10:53 AM Herve Codina <herve.codina@bootlin.com> wrote:
> IRQ 0..7 are not supported by the driver for SPEAr320 SOC family. > > IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT). > Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned > as follow: > IRQ 6 - NGPIO_INTR: Combined status of edge programmable > interrupts from GPIO ports > IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun > IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty > IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun > IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO > IRQ 1 - Reserved > IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports > > Add support for these IRQs in SPEAr320 SOC family. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours, Linus Walleij
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