Messages in this thread | | | Date | Tue, 28 Dec 2021 19:24:11 +0800 | Subject | Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip | From | Yu Tu <> |
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Hi Martin and Jerome, Thank you very much for your reply. I have learned a lot from your communication.
On 2021/12/28 4:04, Martin Blumenstingl wrote: > [ EXTERNAL EMAIL ] > > Hello, > > On Mon, Dec 27, 2021 at 7:56 AM Yu Tu <yu.tu@amlogic.com> wrote: > [...] >>> Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL? >>> If there's still a 24MHz XTAL then I think this description is not >>> correct - at least based on how I understand the UART controller. >>> >> The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode). >> This register description is the same as the G12A and G12B you know. > Thank you for this explanation! > So the problem is that we're not touching bit 26 and bit 27 - and with > the updated romcode you would not get any serial output since the > divider is calculated off the wrong clock. > > I agree with Jerome that we shouldn't put a flag in device-tree. > > Also I did some experimenting with Jerome's idea to implement the > clocks using CCF (common clock framework), see the attached patches. > It was a bit tricky because some initial clean-ups were needed in the > serial driver. > Note: I have only briefly tested this on a 32-bit Meson8m2 SoC, see my > attached patches and the clk_summary debugfs output. > In fact, I expect that there are some issues with at least one of the > patches as the whole bit 26 and bit 27 code is untested. > > Do you see any problems with this patch? > Could you try to implement CCF support with the idea from the attached > patches (you don't need to re-use them, I just wrote them to make it > clearer in our discussion what we're talking about). > I couldn't agree with you more. I have verified it on a 64-bit S4 platform. Please refer to the attachment for verification output information. I will prepare the second version of patch according to the example ideas you provided. > > Best regards, > Martin# cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- xtal 7 7 0 24000000 0 0 50000 Y fe07a000.serial#xtal_div2 1 1 0 12000000 0 0 50000 Y fe07a000.serial#xtal2_clk_sel 1 1 0 12000000 0 0 50000 Y fe07a000.serial#use_xtal 1 1 0 12000000 0 0 50000 Y fe07a000.serial#baud_div 1 1 0 923077 0 0 50000 Y fe07a000.serial#xtal_div3 0 0 0 8000000 0 0 50000 Y fe07a000.serial#xtal_clk_sel 0 0 0 8000000 0 0 50000 Y
# # stty -F /dev/ttyAML0 115200
# stty -F /dev/ttyAML0 speed 115200 baud; line = 0; intr = ^C; quit = ^\; erase = ^?; kill = ^U; eof = ^D; eol = <undef>; eol2 = <undef>; swtch = <undef>; start = ^Q; stop = ^S; susp = ^Z; rprnt = ^R; werase = ^W; lnext = ^V; flush = ^O; min = 1; time = 0; -brkint ixoff -imaxbel
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