Messages in this thread | | | Date | Sat, 25 Dec 2021 11:11:15 +0100 | Subject | Re: [PATCH v1 1/2] RISC-V: Provide a framework for parsing multi-letter ISA extensions | From | Krzysztof Kozlowski <> |
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On 24/12/2021 22:16, Atish Patra wrote: > Recently, there were 15 specifications/40 ISA extensions were ratified. > Except hypervisor ('H') extension, all of them are multi-letter extensions. > Going forward, there will be more number of multi-letter extensions as > well. Parsing all of these extensions from ISA string is not scalable. > Thus, this patch provides a DT based framework to for easy parsing and > querying of any ISA extensions. It facilitates custom user visible strings > for the ISA extensions via /proc/cpuinfo as well. > > Currently, there are no platforms with heterogeneous Linux capable harts. > That's why, this patch supports only a single DT node which can only work > for systems with homogeneous harts. To support heterogeneous systems, this > cpu node must be a subnode for each cpu. > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
Your from address does not match SoB. Please use consistent one - they must match.
Best regards, Krzysztof
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