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    Subject[RFC PATCH v6 2/4] dt-bindings: phy: rockchip: add naneng multi phy bindings
    Date
    From: Yifeng Zhao <yifeng.zhao@rock-chips.com>

    Add the compatible strings for the Naneng multi phy found on Rockchip SoCs.

    Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
    Signed-off-by: Johan Jonker <jbx6244@gmail.com>
    ---

    Changes in v6:
    - change from comb to multi phy
    - add parent node
    - change compatible strings
    - remove rockchip,sgmii-mac-sel
    - remove rockchip,dis-u3otg0-port
    - remove rockchip,dis-u3otg1-port

    Changes in v5:
    - modify description for ssc and ext-refclk
    - remove apb reset

    Changes in v4:
    - restyle
    - remove some minItems
    - add more properties
    - remove reset-names
    - move #phy-cells
    - add rockchip,rk3568-pipe-grf
    - add rockchip,rk3568-pipe-phy-grf

    Changes in v3: None

    Changes in v2:
    - Fix dtschema/dtc warnings/errors
    ---
    .../phy/phy-rockchip-naneng-multiphy.yaml | 167 ++++++++++++++++++
    1 file changed, 167 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-multiphy.yaml

    diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-multiphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-multiphy.yaml
    new file mode 100644
    index 000000000..40ec1b240
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-multiphy.yaml
    @@ -0,0 +1,167 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-multiphy.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Rockchip SoC Naneng Multi Phy Device Tree Bindings
    +
    +maintainers:
    + - Heiko Stuebner <heiko@sntech.de>
    +
    +properties:
    + compatible:
    + enum:
    + - rockchip,rk3566-naneng-multiphy
    + - rockchip,rk3568-naneng-multiphy
    +
    + rockchip,pipe-grf:
    + $ref: /schemas/types.yaml#/definitions/phandle
    + description:
    + Some additional phy settings are accessed through GRF regs.
    +
    + "#address-cells":
    + const: 2
    +
    + "#size-cells":
    + const: 2
    +
    +required:
    + - compatible
    + - "#address-cells"
    + - "#size-cells"
    +
    +additionalProperties: false
    +
    +patternProperties:
    + "multi-phy@[0-9a-f]+$":
    + type: object
    +
    + properties:
    + reg:
    + maxItems: 1
    +
    + clocks:
    + items:
    + - description: reference clock
    + - description: apb clock
    + - description: pipe clock
    +
    + clock-names:
    + items:
    + - const: ref
    + - const: apb
    + - const: pipe
    +
    + resets:
    + items:
    + - description: exclusive PHY reset line
    +
    + rockchip,enable-ssc:
    + type: boolean
    + description:
    + The option SSC can be enabled for U3, SATA and PCIE.
    + Most commercially available platforms use SSC to reduce EMI.
    +
    + rockchip,ext-refclk:
    + type: boolean
    + description:
    + Many PCIe connections, especially backplane connections,
    + require a synchronous reference clock between the two link partners.
    + To achieve this a common clock source, referred to as REFCLK in
    + the PCI Express Card Electromechanical Specification,
    + should be used by both ends of the PCIe link.
    + In PCIe mode one can choose to use an internal
    + or an external reference clock.
    + By default the internal clock is selected. The PCIe PHY provides a 100MHz
    + differential clock output(optional with SSC) for system applications.
    + When selecting this option an externally 100MHz differential
    + reference clock needs to be provided to the PCIe PHY.
    +
    + rockchip,pipe-phy-grf:
    + $ref: /schemas/types.yaml#/definitions/phandle
    + description:
    + Some additional pipe settings are accessed through GRF regs.
    +
    + "#phy-cells":
    + const: 1
    +
    + required:
    + - reg
    + - clocks
    + - clock-names
    + - resets
    + - rockchip,pipe-phy-grf
    + - "#phy-cells"
    +
    + additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/clock/rk3568-cru.h>
    +
    + pipegrf: syscon@fdc50000 {
    + compatible = "rockchip,rk3568-pipe-grf", "syscon";
    + reg = <0xfdc50000 0x1000>;
    + };
    +
    + pipe_phy_grf0: syscon@fdc70000 {
    + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
    + reg = <0xfdc70000 0x1000>;
    + };
    +
    + pipe_phy_grf1: syscon@fdc80000 {
    + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
    + reg = <0xfdc80000 0x1000>;
    + };
    +
    + pipe_phy_grf2: syscon@fdc90000 {
    + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
    + reg = <0xfdc90000 0x1000>;
    + };
    +
    + multiphy: multiphy {
    + compatible = "rockchip,rk3568-naneng-multiphy";
    + rockchip,pipe-grf = <&pipegrf>;
    + #address-cells = <2>;
    + #size-cells = <2>;
    +
    + multiphy0: multi-phy@fe820000 {
    + reg = <0x0 0xfe820000 0x0 0x100>;
    + clocks = <&pmucru CLK_PCIEPHY0_REF>,
    + <&cru PCLK_PIPEPHY0>,
    + <&cru PCLK_PIPE>;
    + clock-names = "ref", "apb", "pipe";
    + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
    + assigned-clock-rates = <100000000>;
    + resets = <&cru SRST_PIPEPHY0>;
    + rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
    + #phy-cells = <1>;
    + };
    +
    + multiphy1: multi-phy@fe830000 {
    + reg = <0x0 0xfe830000 0x0 0x100>;
    + clocks = <&pmucru CLK_PCIEPHY1_REF>,
    + <&cru PCLK_PIPEPHY1>,
    + <&cru PCLK_PIPE>;
    + clock-names = "ref", "apb", "pipe";
    + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
    + assigned-clock-rates = <100000000>;
    + resets = <&cru SRST_PIPEPHY1>;
    + rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
    + #phy-cells = <1>;
    + };
    +
    + multiphy2: multi-phy@fe840000 {
    + reg = <0x0 0xfe840000 0x0 0x100>;
    + clocks = <&pmucru CLK_PCIEPHY2_REF>,
    + <&cru PCLK_PIPEPHY2>,
    + <&cru PCLK_PIPE>;
    + clock-names = "ref", "apb", "pipe";
    + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
    + assigned-clock-rates = <100000000>;
    + resets = <&cru SRST_PIPEPHY2>;
    + rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
    + #phy-cells = <1>;
    + };
    + };
    --
    2.20.1
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