Messages in this thread | | | Date | Mon, 20 Dec 2021 15:46:41 +0530 | From | Pratyush Yadav <> | Subject | Re: [PATCH v2 2/2] mtd: spi-nor: macronix: Add support for mx66lm1g45g |
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Hi Tudor,
On 17/12/21 12:38PM, Tudor.Ambarus@microchip.com wrote: > On 12/17/21 1:38 PM, Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > On 09/12/21 09:04PM, Tudor Ambarus wrote: > >> mx66lm1g45g supports just 1-1-1, 8-8-8 and 8d-8d-8d modes. There are > >> versions of mx66lm1g45g which do not support SFDP, thus use > >> SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral > >> interface outputs data always in STR mode for whatever reason. Since > > > > Huh! I hope this is a mistake from the chip designers, because if it > > isn't they need a stern talking-to ;-) > > > >> 8d-8d-8s is not common, avoid reading the ID when enabling the octal dtr > >> mode. Instead, read back the CR2 to check if the switch was successful. > >> Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP. > > > > Datasheet? > > MX66LM1G45G datasheet: > https://www.macronix.com/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
Thanks.
I see that the RDID waveform holds each byte of the ID for a whole clock cycle. So you would read ab ab cd cd ef ef. I've seen this before somewhere, and sure enough, digging through my inbox I've found this patch [0]. In this read ID is performed but only alternate bytes are compared since they are repeated. I think you should do the same. I feel like reading/comparing 3 bytes is more "robust".
BTW, this patch series also adds support for mx66lm1g45g. You might want to use this as reference.
[0] https://lore.kernel.org/all/20210812150135.4005-2-zhengxunli.mxic@gmail.com/
-- Regards, Pratyush Yadav Texas Instruments Inc.
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