Messages in this thread Patch in this message | | | From | Dario Binacchi <> | Subject | [RFC PATCH 3/4] mtd: rawnand: gpmi: fix controller timings setting | Date | Fri, 17 Dec 2021 16:55:11 +0100 |
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The controller registers are now set accordling to the real clock rate.
Fixes: b1206122069a ("mtd: rawnand: gpmi: use core timings instead of an empirical derivation") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> ---
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c index fd935e893daf..0517b81bb24c 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -648,6 +648,7 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, const struct nand_sdr_timings *sdr) { struct gpmi_nfc_hardware_timing *hw = &this->hw; + struct resources *r = &this->resources; unsigned int dll_threshold_ps = this->devdata->max_chain_delay; unsigned int period_ps, reference_period_ps; unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles; @@ -671,6 +672,8 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; } + hw->clk_rate = clk_round_rate(r->clock[0], hw->clk_rate); + /* SDR core timings are given in picoseconds */ period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); -- 2.32.0
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