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SubjectRe: [PATCH v2 2/2] EDAC/amd64: Add new register offset support and related changes
On Wed, Dec 15, 2021 at 07:07:17PM +0100, Borislav Petkov wrote:
> On Wed, Dec 15, 2021 at 05:32:27PM +0100, William Roche wrote:
> > > @@ -2174,8 +2215,13 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
> > > * There is one mask per DIMM, and two Chip Selects per DIMM.
> > > * CS0 and CS1 -> DIMM0
> > > * CS2 and CS3 -> DIMM1
> > > + *
> > > + * Systems with newer register layout have one mask per Chip Select.
> >
> > Just a question about this comment: Can it be translated into this ?
> >
> > + * Except on systems with newer register layout where we have one Chip Select per DIMM.
>
> Sure, but without the "we":
>
> ...
> * On systems with the newer register layout there is one Chip Select per DIMM.
> */
>

Hi William,
Thanks for the suggestion, but it's not quite correct.

There are still two Chip Selects per DIMM module, i.e. the system can support
dual-rank (2R) DIMMs. Current AMD systems can support upto 2 DIMMs per Unified
Memory Controller (UMC). There are two "Address Mask" registers in each UMC,
and each register covers an entire DIMM (and by extension the two Chip Selects
available for each DIMM).

Future systems will still support upto 2 DIMMs per UMC. However, the register
space is updated so that there are now four "Address Mask" registers per UMC.
And each of these registers is now explicitly related to one of the four Chip
Selects available per UMC.

Does this help? I can update the code comments with these details.

Thanks,
Yazen

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