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    SubjectRe: [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions
    On Fri, Dec 17, 2021 at 01:23:22AM +0800, Rafael J. Wysocki wrote:
    > On Tue, Nov 30, 2021 at 1:37 PM Huang Rui <ray.huang@amd.com> wrote:
    > >
    > > AMD CPPC (Collaborative Processor Performance Control) function uses MSR
    > > registers to manage the performance hints. So add the MSR register macro
    > > here.
    > >
    > > Signed-off-by: Huang Rui <ray.huang@amd.com>
    >
    > I guess I can take this one if there are no objections from the x86
    > maintainers, but it would be nice to receive an ACK from one of them.
    >

    Hi x86 maintainers, the MSR register descriptions are documented at
    Processor Programming Reference (PPR) for AMD Family 19h Model 51h,
    Revision A1 Processors:

    https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip

    Thanks,
    Ray

    > > ---
    > > arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++
    > > 1 file changed, 17 insertions(+)
    > >
    > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    > > index 01e2650b9585..e7945ef6a8df 100644
    > > --- a/arch/x86/include/asm/msr-index.h
    > > +++ b/arch/x86/include/asm/msr-index.h
    > > @@ -486,6 +486,23 @@
    > >
    > > #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
    > >
    > > +/* AMD Collaborative Processor Performance Control MSRs */
    > > +#define MSR_AMD_CPPC_CAP1 0xc00102b0
    > > +#define MSR_AMD_CPPC_ENABLE 0xc00102b1
    > > +#define MSR_AMD_CPPC_CAP2 0xc00102b2
    > > +#define MSR_AMD_CPPC_REQ 0xc00102b3
    > > +#define MSR_AMD_CPPC_STATUS 0xc00102b4
    > > +
    > > +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff)
    > > +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
    > > +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
    > > +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
    > > +
    > > +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0)
    > > +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8)
    > > +#define REQ_DES_PERF(x) (((x) & 0xff) << 16)
    > > +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
    > > +
    > > /* Fam 17h MSRs */
    > > #define MSR_F17H_IRPERF 0xc00000e9
    > >
    > > --
    > > 2.25.1
    > >

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