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SubjectRe: [PATCH v2 2/2] EDAC/amd64: Add new register offset support and related changes
On Wed, Dec 15, 2021 at 05:32:27PM +0100, William Roche wrote:
> > @@ -2174,8 +2215,13 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
> > * There is one mask per DIMM, and two Chip Selects per DIMM.
> > * CS0 and CS1 -> DIMM0
> > * CS2 and CS3 -> DIMM1
> > + *
> > + * Systems with newer register layout have one mask per Chip Select.
>
> Just a question about this comment: Can it be translated into this ?
>
> + * Except on systems with newer register layout where we have one Chip Select per DIMM.

Sure, but without the "we":

...
* On systems with the newer register layout there is one Chip Select per DIMM.
*/

Thx.

--
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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