Messages in this thread | | | Subject | Re: [PATCH v2] perf list: Display hybrid pmu events with cpu type | From | John Garry <> | Date | Wed, 15 Dec 2021 17:34:32 +0000 |
| |
On 15/12/2021 16:18, John Garry wrote:
- yao.jin@linux.intel.com, yao.jin@intel.com
Both these author addresses bounce for me :(
And it's not just my arm64 platform which is damaged, but also my x86 broadwell machine - uncore aliasing for perf list is broken
Before snippet: unc_cbo_cache_lookup.any_es [Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state] unc_cbo_cache_lookup.any_i [Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-state]
After snippet: unc_cbo_cache_lookup.any_es [Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state] unc_cbo_cache_lookup.any_es [Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state] unc_cbo_cache_lookup.any_i [Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-state] unc_cbo_cache_lookup.any_i [Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-state]
Notice how the events are repeated (twice, for each cbox PMU) after, when they should not be.
This seems to be the broken code added in print_pmu_events():
> qsort(aliases, len, sizeof(struct sevent), cmp_sevent); > for (j = 0; j < len; j++) { > /* Skip duplicates */ > - if (j > 0 && !strcmp(aliases[j].name, aliases[j - 1].name)) > - continue; > + if (j > 0 && !strcmp(aliases[j].name, aliases[j - 1].name)) { > + if (!aliases[j].pmu || !aliases[j - 1].pmu || > + !strcmp(aliases[j].pmu, aliases[j - 1].pmu)) { > + continue; > + } > + }
Anyone an idea on the !strcmp(aliases[j].pmu, aliases[j - 1].pmu) check or how to fix it?
Thanks, John
| |