Messages in this thread | | | Date | Tue, 14 Dec 2021 17:22:20 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes |
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On Mon, Dec 13, 2021 at 05:46:55PM +0000, Yazen Ghannam wrote: > Yeah, sorry it's not clear. The purpose of the flag is to indicate some minor > changes that show up with future systems like register offsets changes, etc. I > didn't want to tie the name to a specific model or core name. I went with DDR5 > as a new feature that shows up with these changes, but they're not directly > tied to DDR5. > > But yes, a system may support DDR5 and DDR4. And this can be detected from the > hardware. > > What do you think about calling the flag "uses_f19h_m10h_offsets" or something > like that? I was trying to avoid family/model in the name, but the code > already does this all over. And the convention has been to call something by > the first family/model where it shows up.
Good question.
So AFAIU, these register offset changes are probably going to propagate beyond F19M10... In any case, they won't be tied to the family/model so your flag idea is in the right direction, AFAICT. I'd do something shorter, though, so that the code accessing it is short'n'sweet:
if (pvt->flags.f19h_regs_ng) - "new generation" regs :-)
or even
if (pvt->flags.zn_new_regs_fmt)
or whatever that's called. The GPU UMC is called UMC_v2 so I guess
if (pvt->flags.zn_regs_v2)
:-)
You get the idea...
With an ample explanation in a comment what that means, ofc.
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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