Messages in this thread | | | Subject | Re: [PATCH V4 9/9] arm64: dts: imx8mn: Enable GPU | From | Lucas Stach <> | Date | Tue, 14 Dec 2021 10:24:20 +0100 |
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Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as: > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index d8726d0ce326..5b8f8488e362 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1117,6 +1117,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>;
This repeated CORE and SHADER clock looks odd. Wouldn't it be possible to avoid this by reordering the assigned-clocks?
Regards, Lucas
> + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; > + power-domains = <&pgc_gpumix>; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > -- > 2.32.0 >
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