Messages in this thread |  | | From | Thomas Gleixner <> | Subject | Re: [patch 5/6] x86/fpu: Provide fpu_update_guest_xcr0/xfd() | Date | Tue, 14 Dec 2021 21:28:28 +0100 |
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Juan,
On Tue, Dec 14 2021 at 20:07, Juan Quintela wrote: > Thomas Gleixner <tglx@linutronix.de> wrote: >> On Tue, Dec 14 2021 at 16:11, Wei W. Wang wrote: >>> We need to check with the QEMU migration maintainer (Dave and Juan CC-ed) >>> if changing that ordering would be OK. >>> (In general, I think there are no hard rules documented for this ordering) >> >> There haven't been ordering requirements so far, but with dynamic >> feature enablement there are. >> >> I really want to avoid going to the point to deduce it from the >> xstate:xfeatures bitmap, which is just backwards and Qemu has all the >> required information already. > > First of all, I claim ZERO knowledge about low level x86_64.
Lucky you.
> Once told that, this don't matter for qemu migration, code is at
Once, that was at the time where rubber boots were still made of wood, right? :)
> target/i386/kvm/kvm.c:kvm_arch_put_registers() > > > ret = kvm_put_xsave(x86_cpu); > if (ret < 0) { > return ret; > } > ret = kvm_put_xcrs(x86_cpu); > if (ret < 0) { > return ret; > } > /* must be before kvm_put_msrs */ > ret = kvm_inject_mce_oldstyle(x86_cpu);
So this has already ordering requirements.
> if (ret < 0) { > return ret; > } > ret = kvm_put_msrs(x86_cpu, level); > if (ret < 0) { > return ret; > } > > If it needs to be done in any other order, it is completely independent > of whatever is inside the migration stream.
From the migration data perspective that's correct, but I have the nagging feeling that this in not that simple.
> I guess that Paolo will put some light here.
I fear shining light on that will unearth quite a few skeletons :)
Thanks,
tglx
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