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    Subject[PATCH 5.15 167/171] irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL
    Date
    From: Wudi Wang <wangwudi@hisilicon.com>

    commit b383a42ca523ce54bcbd63f7c8f3cf974abc9b9a upstream.

    INVALL CMD specifies that the ITS must ensure any caching associated with
    the interrupt collection defined by ICID is consistent with the LPI
    configuration tables held in memory for all Redistributors. SYNC is
    required to ensure that INVALL is executed.

    Currently, LPI configuration data may be inconsistent with that in the
    memory within a short period of time after the INVALL command is executed.

    Signed-off-by: Wudi Wang <wangwudi@hisilicon.com>
    Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")
    Link: https://lore.kernel.org/r/20211208015429.5007-1-zhangshaokun@hisilicon.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/irqchip/irq-gic-v3-its.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/irqchip/irq-gic-v3-its.c
    +++ b/drivers/irqchip/irq-gic-v3-its.c
    @@ -742,7 +742,7 @@ static struct its_collection *its_build_

    its_fixup_cmd(cmd);

    - return NULL;
    + return desc->its_invall_cmd.col;
    }

    static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,

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