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    Subject[PATCH 5.10 126/132] irqchip: nvic: Fix offset for Interrupt Priority Offsets
    Date
    From: Vladimir Murzin <vladimir.murzin@arm.com>

    commit c5e0cbe2858d278a27d5b3fe31890aea5be064c4 upstream.

    According to ARM(v7M) ARM Interrupt Priority Offsets located at
    0xE000E400-0xE000E5EC, while 0xE000E300-0xE000E33C covers read-only
    Interrupt Active Bit Registers

    Fixes: 292ec080491d ("irqchip: Add support for ARMv7-M NVIC")
    Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20211201110259.84857-1-vladimir.murzin@arm.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/irqchip/irq-nvic.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/irqchip/irq-nvic.c
    +++ b/drivers/irqchip/irq-nvic.c
    @@ -26,7 +26,7 @@

    #define NVIC_ISER 0x000
    #define NVIC_ICER 0x080
    -#define NVIC_IPR 0x300
    +#define NVIC_IPR 0x400

    #define NVIC_MAX_BANKS 16
    /*

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