lkml.org 
[lkml]   [2021]   [Dec]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
SubjectRe: [net-next RFC PATCH v4 15/15] net: dsa: qca8k: cache lo and hi for mdio write
From


On 12/11/2021 11:57 AM, Ansuel Smith wrote:
> From Documentation, we can cache lo and hi the same way we do with the
> page. This massively reduce the mdio write as 3/4 of the time we only
> require to write the lo or hi part for a mdio write.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/net/dsa/qca8k.c | 49 ++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 44 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> index 375a1d34e46f..b109a74031c6 100644
> --- a/drivers/net/dsa/qca8k.c
> +++ b/drivers/net/dsa/qca8k.c
> @@ -94,6 +94,48 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
> *page = regaddr & 0x3ff;
> }
>
> +static u16 qca8k_current_lo = 0xffff;

Let's assume I have two qca8k switches in my system on the same or a
different MDIO bus, is not the caching supposed to be a per-qca8k switch
instance thing?

> +
> +static int
> +qca8k_set_lo(struct mii_bus *bus, int phy_id, u32 regnum, u16 lo)
> +{
> + int ret;
> +
> + if (lo == qca8k_current_lo) {
> + // pr_info("SAME LOW");

Stray debugging left.

> + return 0;
> + }
> +
> + ret = bus->write(bus, phy_id, regnum, lo);
> + if (ret < 0)
> + dev_err_ratelimited(&bus->dev,
> + "failed to write qca8k 32bit lo register\n");
> +
> + qca8k_current_lo = lo;
> + return 0;
> +}
> +
> +static u16 qca8k_current_hi = 0xffff;
> +
> +static int
> +qca8k_set_hi(struct mii_bus *bus, int phy_id, u32 regnum, u16 hi)
> +{
> + int ret;
> +
> + if (hi == qca8k_current_hi) {
> + // pr_info("SAME HI");

Likewise
--
Florian

\
 
 \ /
  Last update: 2021-12-12 05:05    [W:1.004 / U:0.404 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site