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Subject[PATCH 08/12] arm64: dts: mt8195: Add APU-IOMMU nodes
Date
Add APU-IOMMI nodes.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Flora Fu <flora.fu@mediatek.com>

---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7e31e64e6b39..2f14e3326a2c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/reset/ti-syscon.h>
@@ -1367,6 +1368,22 @@
#mbox-cells = <1>;
};

+ iommu_apu0: iommu@19010000 {
+ compatible = "mediatek,mt8195-iommu-apu";
+ reg = <0 0x19010000 0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ power-domains = <&apuspm 0>;
+ };
+
+ iommu_apu1: iommu@19015000 {
+ compatible = "mediatek,mt8195-iommu-apu";
+ reg = <0 0x19015000 0 0x1000>;
+ interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ power-domains = <&apuspm 0>;
+ };
+
apu_conn: syscon@19020000 {
compatible = "mediatek,mt8195-apu-conn", "syscon";
reg = <0 0x19020000 0 0x1000>;
--
2.18.0
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