Messages in this thread | | | From | Chun-Kuang Hu <> | Date | Fri, 10 Dec 2021 23:44:03 +0800 | Subject | Re: [PATCH] mailbox: add control_by_sw for mt8195 |
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Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年12月10日 週五 下午2:11寫道: > > To make sure the GCE request signal to SPM is not trigger by > other HW modules and cause suspend premature wake. > > Set 0x7 (the bit 0~2 as 1) to GCE_GCTL_VALUE, to configure the > request signal control by SW and release the request to SPM.
How does mt8173, mt8183, and mt6779 prevent this? Or these SoCs could not prevent this?
Regards, Chun-Kuang.
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > drivers/mailbox/mtk-cmdq-mailbox.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c > index a8845b162dbf..342b91f16e65 100644 > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > @@ -664,7 +664,7 @@ static const struct gce_plat gce_plat_v5 = { > static const struct gce_plat gce_plat_v6 = { > .thread_nr = 24, > .shift = 3, > - .control_by_sw = false, > + .control_by_sw = true, > .gce_num = 2 > }; > > -- > 2.18.0 >
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