Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Mon, 8 Nov 2021 16:43:08 +0100 | Subject | Re: [PATCH] clk: renesas: r9a07g044: Add clock and reset entry for SCI1 |
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On Wed, Nov 3, 2021 at 5:05 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add clock and reset entry for SCI1 interface. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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