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SubjectRe: [PATCH v9 3/3] pwm: Add support for Xilinx AXI Timer
Hi Sean,

I love your patch! Yet something to improve:

[auto build test ERROR on thierry-reding-pwm/for-next]
[also build test ERROR on robh/for-next v5.15]
[cannot apply to xilinx-xlnx/master linus/master next-20211108]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Sean-Anderson/microblaze-timer-Remove-unused-properties/20211026-021101
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: microblaze-randconfig-r001-20211027 (attached as .config)
compiler: microblaze-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/e0a4f0ca2ebb0ddd340a3c2de838689ffca33906
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sean-Anderson/microblaze-timer-Remove-unused-properties/20211026-021101
git checkout e0a4f0ca2ebb0ddd340a3c2de838689ffca33906
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=microblaze SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

arch/microblaze/kernel/timer.c: In function 'xilinx_timer_init':
>> arch/microblaze/kernel/timer.c:254:35: error: 'np' undeclared (first use in this function); did you mean 'up'?
254 | if (of_property_read_bool(np, "#pwm-cells"))
| ^~
| up
arch/microblaze/kernel/timer.c:254:35: note: each undeclared identifier is reported only once for each function it appears in


vim +254 arch/microblaze/kernel/timer.c

245
246 static int __init xilinx_timer_init(struct device_node *timer)
247 {
248 struct clk *clk;
249 static int initialized;
250 u32 irq;
251 u32 timer_num = 1;
252 int ret;
253
> 254 if (of_property_read_bool(np, "#pwm-cells"))
255 return 0;
256
257 if (initialized)
258 return -EINVAL;
259
260 initialized = 1;
261
262 timer_baseaddr = of_iomap(timer, 0);
263 if (!timer_baseaddr) {
264 pr_err("ERROR: invalid timer base address\n");
265 return -ENXIO;
266 }
267
268 write_fn = timer_write32;
269 read_fn = timer_read32;
270
271 write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
272 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
273 write_fn = timer_write32_be;
274 read_fn = timer_read32_be;
275 }
276
277 irq = irq_of_parse_and_map(timer, 0);
278 if (irq <= 0) {
279 pr_err("Failed to parse and map irq");
280 return -EINVAL;
281 }
282
283 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
284 if (timer_num) {
285 pr_err("Please enable two timers in HW\n");
286 return -EINVAL;
287 }
288
289 pr_info("%pOF: irq=%d\n", timer, irq);
290
291 clk = of_clk_get(timer, 0);
292 if (IS_ERR(clk)) {
293 pr_err("ERROR: timer CCF input clock not found\n");
294 /* If there is clock-frequency property than use it */
295 of_property_read_u32(timer, "clock-frequency",
296 &timer_clock_freq);
297 } else {
298 timer_clock_freq = clk_get_rate(clk);
299 }
300
301 if (!timer_clock_freq) {
302 pr_err("ERROR: Using CPU clock frequency\n");
303 timer_clock_freq = cpuinfo.cpu_clock_freq;
304 }
305
306 freq_div_hz = timer_clock_freq / HZ;
307
308 ret = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer",
309 &clockevent_xilinx_timer);
310 if (ret) {
311 pr_err("Failed to setup IRQ");
312 return ret;
313 }
314
315 ret = xilinx_clocksource_init();
316 if (ret)
317 return ret;
318
319 ret = xilinx_clockevent_init();
320 if (ret)
321 return ret;
322
323 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
324
325 return 0;
326 }
327

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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