Messages in this thread | | | Date | Mon, 8 Nov 2021 20:19:41 +0800 | From | Leo Yan <> | Subject | Question: SMMUv3 PMU event aliasing |
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Hi John,
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I'd like to confirm the latest upstream status for SMMUv3 PMU event aliasing.
I see the patch set v6 of "perf pmu-events: Support event aliasing for system PMUs" [1] has been landed on the mainline kernel, and as an example, imx8mm DDR PMU has been supported as system PMU [2].
On the other hand, I can see patch set 5 contains the SMMUv3 PMU event aliasing with patch "perf vendor events arm64: Add Architected events smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and it's never landed on the mainline kernel.
Could you share current status (or plan) for upstreaming SMMUv3 PMU event alias? Or if there have any block issue to prevent merging the changes in the mainline kernel?
Thanks for your help!
Leo
[1] https://lore.kernel.org/lkml/1607080216-36968-1-git-send-email-john.garry@huawei.com/ [2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json [3] https://lore.kernel.org/lkml/1604666153-4187-6-git-send-email-john.garry@huawei.com/
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