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    Subject[PATCH AUTOSEL 5.15 55/68] drm/amdgpu: Fix MMIO HDP flush on SRIOV
    Date
    From: Felix Kuehling <Felix.Kuehling@amd.com>

    [ Upstream commit d3a21f7e353dc8d6939383578f3bd45b4ae3a946 ]

    Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset
    to the fixed address of the VF register for hdp_v*_flush_hdp.

    Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Tested-by: Bokun Zhang <bokun.zhang@amd.com>
    Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 ++++
    drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++++
    drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +++-
    drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 ++++
    drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 4 +++-
    drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++++---
    drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++---
    7 files changed, 28 insertions(+), 8 deletions(-)

    diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
    index b184b656b9b6b..a76b5e47e7cbe 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
    @@ -328,6 +328,10 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)

    if (def != data)
    WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
    +
    + if (amdgpu_sriov_vf(adev))
    + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
    + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
    }

    #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
    diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
    index 0d2d629e2d6a2..4bbacf1be25a4 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
    @@ -276,6 +276,10 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)

    if (def != data)
    WREG32_PCIE(smnPCIE_CI_CNTL, data);
    +
    + if (amdgpu_sriov_vf(adev))
    + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
    + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
    }

    static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
    diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
    index 3c00666a13e16..37a4039fdfc53 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
    @@ -273,7 +273,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {

    static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
    {
    -
    + if (amdgpu_sriov_vf(adev))
    + adev->rmmio_remap.reg_offset =
    + SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
    }

    const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
    diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
    index 8f2a315e7c73c..3444332ea1104 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
    @@ -371,6 +371,10 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
    if (def != data)
    WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
    }
    +
    + if (amdgpu_sriov_vf(adev))
    + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
    + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
    }

    const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
    diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
    index f50045cebd44c..9b3f64971a321 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
    @@ -344,7 +344,9 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {

    static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
    {
    -
    + if (amdgpu_sriov_vf(adev))
    + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
    + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
    }

    static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
    diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
    index 01efda4398e56..b739166b242a7 100644
    --- a/drivers/gpu/drm/amd/amdgpu/nv.c
    +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
    @@ -1034,8 +1034,10 @@ static int nv_common_early_init(void *handle)
    #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
    struct amdgpu_device *adev = (struct amdgpu_device *)handle;

    - adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
    - adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
    + if (!amdgpu_sriov_vf(adev)) {
    + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
    + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
    + }
    adev->smc_rreg = NULL;
    adev->smc_wreg = NULL;
    adev->pcie_rreg = &nv_pcie_rreg;
    @@ -1333,7 +1335,7 @@ static int nv_common_hw_init(void *handle)
    * for the purpose of expose those registers
    * to process space
    */
    - if (adev->nbio.funcs->remap_hdp_registers)
    + if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
    adev->nbio.funcs->remap_hdp_registers(adev);
    /* enable the doorbell aperture */
    nv_enable_doorbell_aperture(adev, true);
    diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
    index 0fc97c364fd76..a3361cd68411a 100644
    --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
    +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
    @@ -1136,8 +1136,10 @@ static int soc15_common_early_init(void *handle)
    #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
    struct amdgpu_device *adev = (struct amdgpu_device *)handle;

    - adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
    - adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
    + if (!amdgpu_sriov_vf(adev)) {
    + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
    + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
    + }
    adev->smc_rreg = NULL;
    adev->smc_wreg = NULL;
    adev->pcie_rreg = &soc15_pcie_rreg;
    @@ -1446,7 +1448,7 @@ static int soc15_common_hw_init(void *handle)
    * for the purpose of expose those registers
    * to process space
    */
    - if (adev->nbio.funcs->remap_hdp_registers)
    + if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
    adev->nbio.funcs->remap_hdp_registers(adev);

    /* enable the doorbell aperture */
    --
    2.33.0
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